Fabricating semiconductor devices is a complex process. It involves many steps that require extreme precision and highly pure materials. A semiconductor wafer is provided at an early step in the fabrication process. The wafer serves as a base substrate. Layers of material are added onto the substrate. The shape and composition of the added layers and the substrate are modified to fabricate device components.
A variety of semiconductor devices can be made with a few basic components, such as transistors and capacitors. One widely used device is dynamic random access memory (DRAM). The basic DRAM device is a memory cell having one capacitor and one transistor. The capacitor stores a charge representing data. The transistor allows the data to be written to or read from the capacitor. By reducing the size of its components, semiconductor manufacturers can fit more DRAM devices onto a chip. The increase in the amount of DRAM devices results in greater memory capacity for the chip.
One method of minimizing the size of devices is to vertically construct the components (i.e., where a semiconductor device includes components such as capacitors formed at several or more layers thereof). One way to accomplish such vertical construction may involve forming a trench in a semiconductor substrate. In the process of forming a capacitor, polysilicon (xe2x80x9cpoly-Sixe2x80x9d) may be deposited in the trench as a conducting material or as a sacrificial fill that will be removed during later process steps. The poly-Si may be recessed by removing a portion of the poly-Si through an etching process. Layers of conductive or insulating material may then be deposited in the recessed area of the poly-Si.
The steps of etching the polysilicon and depositing a new composition can be repeated until the desired component is formed. Fabricating components in this manner requires precise control over the process.
Various etching procedures are used to recess poly-Si. One procedure employs reactive ion etching (RIE). RIE is a form of dry etching that may recess poly-Si by bombarding it with charged particles. This type of etching is anisotropic, meaning that when recessing poly-Si in a trench, RIE will etch more in one direction than another direction.
One drawback to RIE is that it is very sensitive to errors in the fabrication process. For instance, the recess depth in a trench depends upon the size of the opening of the trench. With RIE in general, the wider the trench opening, the shallower the recess depth for a given etch time. If the masks used to create multiple trenches vary in size due to normal process fluctuations, using RIE can result in different poly-Si recess depths for different devices on the same substrate. This amounts to even less control over the etching process.
Another drawback to RIE is that only a few wafers can be etched at one time. This results in a low yield that drives up the cost of producing semiconductor devices. Therefore, there is a need for a high yield alternative etch process that gives the manufacturer better supervision over the etching process and greater control overall.
Yet another drawback to RIE is that it is not a very selective process. Selectivity is the ratio of the etch rate of one material as compared to the etch rate of another material. For example, in an etching step to remove poly-Si from a trench having an oxide collar, poor selectivity could mean that nearly as much oxide is removed as poly-Si. If too much of the oxide collar is removed, the component formed in the trench may be unusable. Therefore, poor selectivity takes away some of the manufacturer""s control over the etching process. RIE has a selectivity of about 50:1 when comparing the etch rates of poly-Si and silicon dioxide (xe2x80x9cSiO2xe2x80x9d). This means that RIE is fifty times more effective at etching poly-Si than it is at etching SiO2. Similarly, RIE has a selectivity of about 10:1 when comparing its etch rates for poly-Si and silicon nitride (xe2x80x9cSiNxe2x80x9d).
The present invention solves the problems associated with RIE by replacing RIE with a highly efficient wet chemical etching process. The present process uses a solution of ammonium hydroxide (xe2x80x9cNH4OHxe2x80x9d) in water to etch poly-Si. The solution of NH4OH and water is isotropic, meaning that it etches equally in all directions, yet it has a very high selectivity between poly-Si and other materials. For example, NH4OH has a typical selectivity of about 9,000:1 when comparing the etch rates of poly-Si to SiO2. NH4OH has a typical selectivity of about 50,000:1 when comparing the etch rates of poly-Si to SiN.
The etch rate can be controlled by altering the concentration, temperature and/or exposure time of the solution. Unlike RIE, the present wet chemical etching process is more cost efficient than RIE because many wafers can be etched simultaneously using relatively inexpensive chemicals. Furthermore, the present invention is relatively unaffected by trench dimension errors (e.g., where the trench dimensions are larger or smaller than specified). This is because the present wet chemical etching process generates new etch chemicals (e.g., hydroxyl ions) even in the bottom of the trench. These new etch chemicals prevent chemical depletion and allow the poly-Si to be etched to a desired depth.
In the past, solutions containing NH4OH, water and other chemicals such as hydrogen peroxide have been used to remove surface contaminants while cleaning semiconductor devices during the fabrication process. However, a solution of NH4OH and water has not previously been used to recess poly-Si. That is because cleaning solutions may contain oxidizing chemicals such as H2O2. These oxidizing chemicals may passivate the surface of the poly-Si with SiO2 films, thereby inhibiting the etching process.
In accordance with one example of the present invention, a method is provided for fabricating a semiconductor device on a semiconductor substrate. As used herein, the term xe2x80x9csubstratexe2x80x9d is intended to include semiconductor wafers made of silicon, other elements or compound semiconductors (e.g., substrates formed from a combination of materials). It is also intended to include semiconductor wafers that have been processed in some manner so that additional materials may have been deposited or formed thereon. Furthermore, the term xe2x80x9cpoly-Sixe2x80x9d as used herein is intended to include all forms of silicon including, but not limited to crystalline silicon, epitaxial silicon and amorphous silicon. The poly-Si may include a dopant (e.g., arsenic, phosphorous or boron), and other materials may be associated with it (e.g., germanium may be added to the poly-Si to form silicon-germanium).
The semiconductor device fabricated in accordance with the present method may comprise a poly-Si region having a first dimension. In one embodiment, the method comprises first applying a solution comprising NH4OH in water to the poly-Si region. The solution is used to etch the poly-Si to obtain a second dimension of a desired shape and size.
The etch rate of the method may be adjusted by varying one or more parameters of the solution. For example, one parameter that may be adjusted is the concentration of the solution. In a preferred embodiment, the concentration of NH4OH to water may vary from a ratio of 1:2 to 1:200 (NH4OH:H2O). In another preferred embodiment, the concentration may be between 1:5 and 1:80. In yet another preferred embodiment, the concentration may be between 1:5 and 1:50. The foregoing concentration ranges are approximate, and the concentration may be slightly higher than the upper limit or slightly lower than the lower limit of such ranges.
The etch rate of the present method may also be adjusted by varying the temperature of the solution. The temperature may range between 25xc2x0 C. and 65xc2x0 C. This temperature range is also approximate. Thus, in preferred embodiments, the temperature may be slightly more than 25xc2x0 C. or slightly less than 65xc2x0 C.
In another preferred embodiment, the temperature may be between 25xc2x0 C. and 45xc2x0 C. In yet another preferred embodiment, the concentration of the solution may be between 1:5 and 1:80 while the temperature may be between 25xc2x0 C. and 45xc2x0 C. In yet another preferred embodiment, the temperature is held substantially constant by employing a convolution bath. In yet another preferred embodiment, the solution is degasified. The manufacturer maintains excellent control over the etching process by choosing the temperature, concentration and application time sufficient for a desired etch rate.
In accordance with another example of the present invention, a method is provided for fabricating a semiconductor device. Initially, a trench is formed in a semiconductor substrate. The trench may have lower and upper regions. Next, poly-Si may then be deposited in the trench. In a preferred embodiment, the poly-Si may substantially fill the lower and upper regions of the trench. However, it should be appreciated that the amount of poly-Si deposited in the trench may vary in accordance with the desired structure and operation of the semiconductor device being fabricated. The poly-Si is preferably doped, either with n or p type dopant. The extent of doping can vary widely in accordance with design choices. A first solution comprising NH4OH in water is then applied to the poly-Si. The first solution is used to etch a portion of the poly-Si to recess the poly-Si to a desired shape and size.
In a preferred embodiment, the method of fabricating a semiconductor device may include several steps in addition to those described above. For example, a collar oxide may be formed in the upper region of the trench before the poly-Si is deposited. SiN may then be deposited in the upper region of the trench after the portion of poly-Si is etched with the first solution of NH4OH in water. Next, a portion of SiN may be etched from a bottom of the upper region. Then, a second solution of NH4OH in water may be applied to the poly-Si. The second solution may have the same or different concentration and temperature as the first solution. The second solution is used to etch a second portion of the poly-Si in the lower region of the trench. This results in the trench having a bottle shape, with the lower region being wider than the upper region.
The method of fabricating a semiconductor device may also include the additional procedure of performing RIE after the SiN is deposited. Etching by a RIE process removes at least a portion of the SiN in the bottom of the upper region. It may also remove another portion of the poly-Si that is in the lower region of the trench. RIE may be used to remove a seam, if any exists, in the lower region of the trench.
In accordance with another example, the first and second solutions of NH4OH in water may have a concentration between 1:5 and 1:80. Additionally, the first and second solutions preferably have a temperature between 25xc2x0 C. and 65xc2x0 C. As stated previously, these ranges are approximate and may be slightly more or less than these maximums and minimums. Also, in this example the first and second solutions are preferably degasified.
In accordance with another example of the present invention, a method is provided for fabricating a semiconductor device having multiple components on a substrate. Initially, at least one layer of material is added onto the substrate. The material preferably comprises a doped (either n or p type) semiconductor. However, in alternative embodiments, the material may comprise conductors or insulating compositions. Then, a solution of NH4OH in water is applied to the at least one layer. The solution is used to etch the material to obtain a desired shape and size.
Other steps may be employed in embodiments of the method for fabricating the semiconductor devices. The steps of adding additional layers, applying the solution, and etching may be repeated until the desired semiconductor device is fabricated. Preferably at least one of the layers of material comprises poly-Si. The solution may be refreshed to maintain a desired etch rate.
The method of the present invention may be used to fabricate a variety of semiconductor devices. The foregoing aspects, features and advantages of the present invention will be further appreciated when considered with reference to the following description of the preferred embodiments and accompanying drawings.